Bonnell microarchitecture

Intel Atom processors are based on the Bonnell microarchitecture34 which can assassinate up to two instructions per cycle. Like abounding added x86 microprocessors, it translates x86-instructions (CISC instructions) into simpler centralized operations (sometimes referred to as micro-ops, i.e., finer RISC appearance instructions) above-mentioned to execution. The majority of instructions aftermath one micro-op back translated, with about 4% of instructions acclimated in archetypal programs bearing assorted micro-ops. The cardinal of instructions that aftermath added than one micro-op is decidedly beneath than the P6 and NetBurst microarchitectures. In the Bonnell microarchitecture, centralized micro-ops can accommodate both a anamnesis amount and a anamnesis abundance in affiliation with an ALU operation, appropriately actuality added agnate to the x86 akin and added able than the micro-ops acclimated in antecedent designs.19 This enables almost acceptable achievement with alone two accumulation ALUs, and after any apprenticeship reordering, abstract execution, or annals renaming. The Bonnell microarchitecture accordingly represents a fractional awakening of the attempt acclimated in beforehand Intel designs such as P5 and the i486, with the sole purpose of acceptable the achievement per watt ratio. However, Hyper-Threading is implemented in an accessible (i.e., low power) way to apply both pipelines calmly by alienated the archetypal distinct cilia dependencies